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Many aspects of today’s modern society are enabled by advances in semiconductor technologies. Most of those innovations have been driven by the incumbent corporates in the industry but some of them have come from ambitious startups globally. Despite the size of the market and the potential for key innovation, startups active in semiconductor technologies have often struggled to raise sufficient capital in the past decade, even in times when other sectors of the venture capital market have been very active. Since one to two years, though, we start to see a change in sentiment of venture capital investors towards semiconductor technology startups. This is driven by external market factors, such as the onset of artificial intelligence technology, driving global increase of data center traffic and compute performance, as well as geopolitical considerations and dependencies.imec.xpand is one of the world’s largest independent venture capital funds dedicated to early-stage semiconductor innovation. Since 2018 we have been investing in ambitious startups where the knowledge, expertise and infrastructure of imec, the world-renowned semiconductor and nanotechnology R&D center, can play a determining role in their growth. imec.xpand has an outspoken international mindset towards building disruptive global companies and strongly believes that sufficient funding from the start is key to future success. Our position gives us a unique view on the startup landscape in the sector, which we will share with the audience.

The fate of LCoS micro display panels for AR devices seems to be re-written every year, its demise being push further away by every new smart glass release. A decade ago, with the first microLED start-ups acquisitions by large corporations developing smart glasses (Apple, Facebook), the immediate future looked quite promising for this technology. 10 years later, the facts are telling a different story: the largest smart glass manufacturers are now using microOLED panels with birdbath architectures, while LCoS or DLP panels as well as MEMS DLP scanners are still the display engine of choice for all waveguide combiner smart glass architectures. So where are the microLED panel we were promised a decade ago?
First, LCoS is a technology undergoing successive incremental improvements from power to resolution to contrast to uniformity. It is a well matured technology that can be scaled at 12 inch wafer fab at low cost compatible with consumer products. Moreover, new illumination technologies allow for further LCoS light engine size reduction (front lit panels) and additional power savings (local dimming illumination and color flex operation modes). LCoS is also providing solutions for holographic display, and various other applications as in DWDM all optical switching and free space laser communications. Second, RGB microLED technology has not yet found its standard technology form yet, although industry went away from the early pick and place processes. Today, various architectures are still being tried out such as QD or Perovskites conversion, nanowires with PC effects and true monolithic integration over Silicon substrates, along with other exotic color tuning technologies. However, no matter how long it will take, microLED is still poised by industry and analysts to the best display choice for future smart glasses.

Ultrafast laser technology is at the forefront of driving miniaturization and precision across various markets, including consumer electronics, semiconductors, and healthcare. In this presentation, we will explore the potential of ultrafast laser processing for advancing microLED technology. We will share our insights and experiences in laser applications that could be relevant to microLED development, such as processing transparent and polymer substrates, selective laser deposition, and other techniques. Additionally, we aim to identify and address the unique challenges presented by the microLED market using our laser technology solutions.

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Focal Plane Array (FPA) imaging and detector devices, such as infrared (IR) thermal imaging sensors, Quantum computing processors and micro LED displays are seeing higher demand as more practical applications requiring these components are coming into research and development, military, industrial and consumer markets. This paired with higher pixel and Qubit count and interconnect density on larger and larger chips is driving hybridization and monolithic integration in these technologies. This is showing a marked increase in demand for fine pitch micro Indium Bump Interconnect (IBI) flip chip die bonding. However, some critical challenges facing these technologies are: larger component sizes mean higher density interconnections over increasing surface area. Sub-micron accuracy is required to align fine pitch micro interconnect arrays. This together with the challenges facing the materials that are becoming the industry standard for these applications, such as the requirement for the assembled components to remain stable in extreme conditions such as cryogenic application environments, combined with low loss high strength mechanical / electrical interconnect requirements on components containing sensitive materials, structures and unmatched coefficient of thermal expansion (CTE) means that processing gases such as formic acid or high temperature reflow bonding can no longer be used to bond these devices. These challenges mean that the industry is fast approaching the limitations of even state-of-the-art die bonders and die bonding methods on the market today. This paper is going to highlight these challenges and the methods used to address them to produce large format, high density Infrared (IR) thermal imaging devices, Quantum processors and micro LED displays using fine pitch micro Indium Bump Interconnections (IBI) that meet today's industry requirements.

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The presentation gives an introduction to development of anisotropic conductive film suited for mini and micro LEDs. The technology use the same principles as already existing films for larger footprint components. Conductive particles are mixed into a liquid acrylic monomer resin and aligned in a grid of particle strings using an electrical field. While aligned in the E-field the resin is cured, fixing the particles in place and forming an anisotropic double-sided tape ready for use by customers. The presentation will also address manufacturing challenges to be solved and also how such product can be used to bond mini and micro LEDs.

LED manufacturing is a complex and technically challenging process. very few companies worldwide operate across all segments of the value chain. The areas of specialization and expertise existing in the industry break down the value chain for LED manufacturing into three large segments, i.e., substrate production, LED die fabrication and packaged LED assembly. As micro-LED takes a core importance due to immense energy-saving benefits there is a push to upscale to 8-inch LED epitaxy and consequently 8-inch substrate platform. This is to achieve surface-area multiplier, and accordingly, the yield multiplier benefits in the LED die fabrication process. Sapphire crystal-based substrate indicates specific advantages over other substrate materials regarding the balance of lattice match and cost competitiveness for LED epitaxy application. However, the Sapphire crystal growth in the substrate production is one of the most energy intensive processes in the entire LED production chain with an energy contribution of 160.46 kWh per 8-inch wafer with the conventional Kyropoulos growth process employed in Asia. This is equivalent to a CO2 emission of 96.27 kg per wafer. At FAMETEC GmbH in Austria, a highly energy-efficient technology named as McSap (Multi-Crystal-Sapphire) growth has been developed that brings down the energy contribution to 28.16 kWh per 8-inch wafer and the equivalent CO2 emission to 10.00 kg per wafer. This is equivalent to 89.61% decrease in CO2 emission in sapphire substrate wafers produced in Europe when compared to the emission produced from the prevalent technology in Asia. The dramatic reduction in environmental footprint is achieved by a leading-edge thermal design of McSap simultaneous growth of multiple sapphire crystals along the crystal axis in 8-inch cylindrical volumes eliminating the need for the wasteful coring and grinding steps typically required in traditional growth methods. Which led to the increase in the yield of usable, high-quality sapphire material.

Producing indium bumps for interconnect is a technology that has had to adapt to an ever increasing demand for smaller bump size and high bump density while having to process larger and larger substrate sizes. This presentation discusses how indium bump fill and uniformity was optimized for substrates up to 200mm wafers. We demonstrate strategies to both prevent dendritic growth, to produce reliable bumps, and to eliminate indium spits, which can be a source of defects, without having to sacrifice tack time and reliability.

This talk will explore the limitations in hexagonal GaN LED devices for longer wavelength microLEDS and the opportunity to develop the cubic form of GaN into the de facto solution for microLEDs, not only in the red wavelengths, but also for RGB solutions. Cubic GaN is the current state-of-the-art solution for this market and offers a manufacturing route that is not only similar to existing GaN LED epitaxial manufacture, using MOCVD, but also scalable to 300mm in the future.

The rapid implementation of Mini and MicroLED lighting technologies has promoted innovation in every aspect of the SMT assembly process. Printing, placement, and reflow are all impacted when these assemblies are performed. The main challenge posed by this type of assembly is simply the scale of the components. The dimensions involved are below the visual threshold for most human beings. One of the biggest challenges for assembly in this sector involves the printing of solder paste. Tens, if not hundreds of thousands of ultra-miniature deposits must be made with micron precision in a single stroke of a squeegee. Furthermore, his needs to be accomplished at production speed and scale without room for error. In this presentation, we share our knowledge and solutions acquired as one of the largest solder suppliers in the world to the Mini and MicroLED market.

Since the development of the blue LED in the latter years of last century, LED technology has revolutionised the display industry. Now with demands for small high resolution displays used for AR/VR/XR applications and as a competitor to OLEDs for use in watches and mobile phones, a concerted effort is being made to transfer this technology to the much smaller microLEDs, with typical dimensions in the range of 1 to 10 microns. This transfer is far from straightforward as size effects begin to dominate. Our discussion herein has explored various etching methodologies for GaN and AlInGaP mesas, isolation, and pillar etching related to LED or microLED applications. The excellence of these etching processes holds paramount importance in shaping the ultimate performance of microLED devices. Our presentation will elucidate strategies for achieving well controlled profile angles, smooth surface, and sidewall with optimised processes. OIPT has an ongoing programme investigating correction of size effects, for the transition to the smallest devices <5 microns, where the damage in sidewalls begins to dominate in a way that is not seen in typical larger devices.

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MicroLED technology holds immense promise for augmented reality (AR) displays, but its widespread adoption still faces manufacturing challenges. This presentation will discuss proposed solutions to fabrication of MicroLED microdisplays, exploring issues related to yield, scalability, and efficiency.

Micro-LEDs are a major advancement in visual display technology, offering high brightness, efficiency, and long lifespan. However, their high cost stems from low-yield fabrication processes that struggle to reliably connect millions of microscopic LEDs to the display backplane. Faulty pixel identification, repair strategies, and dual redundancy have enabled the production of working displays with superior image quality due to their high dynamic range. However, inspection only identifies issues; it doesn’t resolve them, and repair costs time and money. Therefore, there is a need to enhance micro-LED fabrication quality through innovative processes.

This presentation introduces a chip-first strategy, where micro-LEDs are placed face down on a substrate with contact pads facing upwards. A pre-polymer layer is spin-coated, patterned, and cured to form via hole connections above the anode and cathode pads. A metal layer is then sputtered and patterned to connect the LEDs, without using eutectic bonding or laser sintering. Organic thin-film transistor (OTFT) materials are applied in multiple layers using conventional tools, yielding a high-quality display through low-temperature processes (<150°C). The low temperature prevents damage to micro-LEDs, is eco-friendly by using less energy, and allows the use of a wider range of transparent plastic substrates with better optical qualities. The lowest temperature tested so far is 80°C. The presentation will show the structure of the chip-first backplane and its corresponding cross-sectional structure. OTFT transfer curves and an image of the 100x180 monochrome 2.2” display are also presented. Turn-on yield of the wired-up micro-LEDs is high, with no failures detected in over 18,000 devices.

In recent years, there has been a significant surge in the adoption of micro-LED-based display technology by major industry players. However, the current assembly process faces fundamental bottlenecks. While state-of-the-art pick-and-place equipment can process over 60,000 units per hour (UPH), the technique is ill-suited when it comes to assembling micro-components with dimensions smaller than 100 μm. Furthermore, with the high number of microLEDs per display, there is a need to accelerate the assembly process. Take, for instance, the current high-end smartphone display, which would need about 10 million microLEDs – this would require a traditional pick-and-place machine a week to assemble. Additionally, defect management for dead pixel-free displays requiring accurate and fast placement of a single die is also currently a challenge. Due to these bottlenecks, manufacturers are actively exploring alternative cost-effective, accurate, and fast assembly solutions. Holst Centre has developed an innovative and proprietary release stack that enables the fast release of micro-LED-sized components with an adaptive pitch and high selectivity using a low-cost laser source. Our technology exhibits exceptional scalability and flexibility, facilitating the transfer of both mini- and microLEDs. In an R&D environment at Holst Centre, we achieved a remarkable microLED transfer precision with displacements of 1µm (1σ) and rotations of 1° (1σ), coupled with a yield surpassing 99.9% on a sample set with over ten thousand components. This advancement not only enables defect management but also offers compatibility with die-on-demand release from ultrahigh-density wafers, achieving edge-to-edge die spacing down to just a few micrometers. The transfer of microcomponents to our release stack relies on a lamination process utilizing a temporary carrier. There is a difficulty in procuring micro-LEDs due to their limited commercial availability during development, a problem that is further exacerbated by the absence of standardization in microLED sizes and buildup architecture. The microLEDs have a diverse range of architectures, form factors, and sizes, introducing additional complexity to the systematic testing of this technology. Therefore, we have developed a new process of monolithically fabricating ultrasmall dummy dies on our proprietary release stack which can be transferred via a laser. The use of this new process enables precise and accurate fabrication of dummy dies with varying sizes, aspect ratios, and adaptive pitches — matching form factors and dimensions of various microLEDs.

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Emerging MicroLED technology offers compelling potential for near-eye devices. However, the MicroLED supply chain currently lacks readiness for mass production due to significant manufacturability and cost challenges. For near-eye device applications, this technology requires ultra-fine pixels (<10 micrometers) and highly miniaturized silicon transistors on the backplane. A heterogeneous integration approach adopted from a 3-D semiconductor system can address many MicroLED process technology, design, and cost challenges. This talk is concerned with two main strategies for drastic cost reduction: (1) lowering the cost of individual LEDs through the monolithic fabrication of GaN RGB diodes on a 300 mm silicon wafer, and (2) decreasing frontplane-to-backplane integration costs using wafer-to-wafer bonding, specifically bonding a 300 mm RGB wafer to a 300 mm silicon CMOS wafer. Our presentation will explore these strategies from the perspective of cost-effective and scalable semiconductor system integration, leveraging the mature 300 mm high-volume-manufacturing supply chain extensively used in the semiconductor industry for about 25 years, incorporating high-performance and low-power CMOS design for backplane devices, and utilizing recent advancements in 3-D heterogeneous integration with hybrid bonding.